Ethernet network devices include physical layer devices that transmit and receive data over a medium. In a gigabit (Gb) network device, the physical layer device includes a physical coding sublayer (PCS), which acts as an interface between (i) a gigabit media independent interface (GMII) or an extended GMII (XGMII) and (ii) a physical medium attachment (PMA) layer.
The PCS typically includes an encoder and a decoder. The PCS may also include other components such as a scrambler and a gearbox. The gearbox is not necessary when an analog circuit in the PMA layer is designed to run based on (i) multiples of a reference clock, or (ii) multiples of a bus width. In essence, the gearbox is used as a digital solution to overcome analog circuit limitations. The encoder provides data formatting and organizes the data into bytes of data and control codes. Encoding performed by the encoder may be referred to as 64/66 bit encoding, where 64 bits are provided to the encoder and 66 bits are output from the encoder. The 66 bits include a 2-bit synchronization (SYNC) header. The scrambler performs line balancing and ensures sufficient transition density. This may include providing a relatively even distribution of 1s and 0s in an output of the scrambler. The function of the gearbox is application specific. The gearbox may include a buffer that is used to adjust for input and output speed differences of the gearbox. The gearbox may format data widths for a serializer/deserializer (SERDES). For example, the gearbox may convert the 66 bit signal to a 16 bit interface signal. The SERDES may then convert this 16 bit interface signal into a fully serial signal. The gearbox may combine the 2-bit sync header with the output of the scrambler.
A PCS may be implemented based on the 10GBASE-R standard described in Institute of Electrical and Electronics Engineers (IEEE) section 802.3, which is hereby incorporated herein by reference. The 10GBASE-R standard implements 64/66 bit encoding, which has low overhead. The 10GBASE-R standard restricts placement of control codes within an encoded block. This prevents encoding aggregated bytes of data and control codes, received from multiple independent communications channels, when the bytes of data and control codes are not received in a predetermined order. Bytes of data and control codes are received in a predetermined order when the control codes are in certain positions relative to the bytes of data. In other words, an encoder, designed according to the 10GBASE-R standard, may be unable to encode bytes of data and control codes that are received in an arbitrary or unknown order.